Synchronizers receive data from upstream logic in one clock domain and synchronize that data to another clock domain associated with logic downstream of the synchronizer. The synchronizer ensures that the data coming out of the synchronizer will not violate the setup or hold constraints of clocked elements located downstream of the synchronizer. During synchronization, it is possible for the incoming data to violate the setup or hold constraints of the synchronizer itself, and thereby cause a meta-stable condition to occur in the synchronizer. The amount of time that it takes for the synchronizer to exit this meta-stable state and move towards a valid state is commonly referred to as the resolving time of the synchronizer. It is desirable to minimize the resolving time of the synchronizer so that the speed of the synchronizer can be maximized and so that the possibility of a synchronizer failure occurring can be minimized.
FIG. 1 is a schematic diagram of a synchronizer that is currently used in integrated circuits. The synchronizer 1 comprises a master latch 2 and a slave latch 3. The master latch 2 and the slave latch 3 both have resolving times associated with them. Generally, the master latch 2 is allowed to use one-half of the clock cycle to resolve an incoming value of the data, D, and the slave latch 3 is allowed to use the second half of the clock cycle to resolve the signal received from the master latch. During a single clock cycle, the data D is transferred into the master latch 2, is transferred from the master latch 2 to the slave latch 3 and is output as output Q from the slave latch 3 for use by logic located downstream of the synchronizer 1.
A synchronizer failure occurs when the functions performed by the master latch 2 and the slave latch 3 fail to resolve the value of the data D to a logic 0 or 1 by the end of the clock cycle. If the output Q has not been resolved to a 1 or a 0 by the end of the clock cycle, the downstream logic will receive a value that is between a logic 0 and a logic 1 and this intermediate value may be erroneously interpreted by the downstream logic. Therefore, it is crucial to minimize the likelihood of a synchronizer failure occurring.
FIG. 2 illustrates a timing diagram of the wave forms of the clock signals M1 and S1 of the master latch 2 and slave latch 3, respectively. The clock signals M1 and S1 are inverses of one another. For a positive edge-triggered synchronizer, the clock signal S1 is the clock directly and the clock signal M1 is the clock inverted. Thus, the output Q will change on the rising edge of the clock, which is when the transfer gate T4 turns on and allows the value on node MAS of the master latch 2 to be transferred to the slave latch 3. As shown in FIG. 2, S1 goes low just before M1 goes high. If M1 were to go high while S1 was high, the value of the data signal D would simply pass through the synchronizer 1 without waiting for the clock to change, and the data would not be synchronized to the new clock domain.
During normal operation, when M1 is high, the transfer gate T1 is turned on and the data signal D is passed to the storage node SN1. The data signal D passes through a forward inverter I2 and then through a feedback inverter I3 to the storage node SN1. The inverter I3 provides a small amount of gain sufficient to hold the value of the signal on the storage node SN1. When M1 goes low, T3 turns on and another feedback inverter, 11, which is a relatively strong feedback inverter, provides additional gain to the signal fed back to the storage node SN1. This additional gain serves to drive the value of the signal on node SN1 during the period when M1 is low and is not driving the data signal.
S1 goes high when M1 goes low, thereby turning gate T4 on, and the signal on node MAS is transferred into the slave latch 3. While S1 is high and M1 is low, the master latch 2 is attempting to resolve the value on node SN1 to a 1 or a 0. The signal on node SN2 passes through forward inverter 15 and is fed back through feedback inverter 16 to the storage node SN2. Both of these inverters apply gain to the signal. The gain provided by inverter 16 holds the value on node SN2. When S1 goes low, gate T5 is turned on and feedback inverter 14 feeds back the signal from node SLV to node SN2, while providing additional gain to the signal.
In the master latch 2, the gain provided by the feedback inverters I1 and I3 and the gain provided by the forward inverter I2 facilitate the resolving process by helping to drive the values on nodes SN1 and MAS to a 0 or a 1. Likewise, the inverters I4, I5 and I6 of the slave latch 3 provide gain that helps to drive the values on nodes SN2 and SLV to a 1 or a 0. If the value of the data D is transitioning near the time when M1 goes low, a meta-stable state can occur in the master latch 2. A particular value exists between 0 and 1 that will cause the master latch 2 to be put in a meta-stable state if transistor T1 is turned off at the time that the particular value is on node SN1.
If this meta-stable state has not been resolved by the time that S1 goes low, then the slave latch 3 will attempt to resolve this meta-stable condition. The amount of time that it takes the master latch 2 to begin driving the value on node SN1 toward a logic 0 or 1 from the meta-stable value is known as the resolving time of the master latch 2. Typically, the resolving time is viewed as the amount of time that it takes for the voltage on node SN1 to change by a factor of e, which is a well known constant having a value of 2.718.
The probability that a meta-stable value will be output from the synchronizer 1 at output Q is a function of several factors. As stated above, the master latch 2 has one-half of the clock cycle (i.e., while S1 is high) to resolve the value of D to a 0 or 1 because the value should be resolved by the time that the slave latch 3 is turned off. Similarly, the slave latch 3 has one-half of the clock cycle (i.e., while S1 is low) to resolve the value on node SN2 because the value output at Q should be resolved to a 1 or a 0 by the end of the clock cycle if the synchronizer is driving directly into another register. If additional logic exists between the synchronizer and the next register, then the time it takes to pass through that logic will need to be subtracted from the time that the slave latch has to resolve.
Although the design of the synchronizer 1 shown in FIG. 1 generally has a good resolving time associated with it, it would be desirable to provide an improved synchronizer design that would further reduce the resolving time and that would minimize the likelihood of a synchronizer failure occurring. One of the disadvantages associated with the synchronizer 1 is that when S1 goes high and M1 goes low, node MAS of the master latch 2 sees the capacitance associated with node SN2 of the slave latch 3. Since the master latch 2 is resolving when M1 is low and S1 is high, the capacitance on node SN2 that is seen by node MAS limits the resolving speed of the master latch 2. The capacitance on node SN2 is the capacitance associated with gate T5 and with inverters 15, 16 and 17. This total capacitance is relatively large and significantly limits the speed with which the master latch 2 can resolve to a 0 or a 1.
Another disadvantage of the synchronizer 1 shown in FIG. 1 is that the input stage T1 of the master latch 2 and the input stage T4 of the slave latch 3 provide no gain to the signals being input to these latches. Consequently, these input stages do not reduce the probability that the latches will see a meta-stable value on their storage nodes.
Another disadvantage of the design of the synchronizer 1 shown in FIG. 1 is that, during testing of the synchronizer 1, both of the feedback inverters I1 and I3 of the master latch 2 must be overdriven by the transfer gate T2. During testing of the synchronizer 1, data is scanned into the synchronizer 1 via a serial test port, which is represented by SCANNIN in FIG. 1. A plurality of synchronizers are connected together to form a shift register by connecting the output Q of each synchronizer to the SCANNIN input of another synchronizer. The SHIFT signal is then utilized to control the transfer gate T2 in order to allow data to be shifted into the master latch 2. Logic (not shown) coupled to gate T4 controls the shifting of the data from the master latch 2 to the slave latch 3.
Essentially, the SHIFT signal and the signal being used to control the gate T4 are alternatively toggled in order to shift the data into the master latch during the first half of the shift cycle and to shift the data into the slave latch during the second half of the shift cycle. A test signal is used to force M1 low so that transfer gate T1 is turned off during testing. Since gate T3 is controlled by M1 inverted, gate T3 is turned on during testing, thereby rendering inverter I1 operational. Consequently, both of the feedback inverters I1 and I3 must be overdriven by gate T2 during testing, which requires that the gate T2 be sufficiently large to overdrive these inverters. However, making gate T2 large increases the capacitance on node SN1 of the master latch 2, which, in turn, limits the speed with which the master latch 2 can resolve the data signal D to a 0 or a 1.
Accordingly, a need exists for a synchronizer that overcomes the limitations associated with the synchronizer 1 shown in FIG. 1 and that has improved resolving ability in terms of both an increased resolving speed and a decreased likelihood that a synchronizer failure will occur.